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In view of the problem that embedded software cannot meet the real-time processing speed of digital image, the idea of hardware accelerator is proposed to realize the optical flow field target detection algorithm on Field Programmable Gate Array (FPGA). By parallel processing data and pipeline design, the processing speed of algorithm is greatly improved. The modular hardware design method is adopted to ensure the portability and scalability of the system. Finally, the algorithm is processed by verilog programming, and is simulated and verified on ZedBoard.
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